The present invention relates to data retention in a random access memory (DRAM). More specifically, the present invention relates to guaranteeing data retention in a DRAM employed in a system which decreases the DRAM power supply voltage when the DRAM is in a standby state, such as a power save mode or a battery backup mode, to reduce power consumption.
In recent years, more electronic devices, such as personals computers incorporating DRAMs, use batteries as power sources. Power consumption in such electronic devices must be decreased in order to increase the operation time of the electronic device or to decrease the required capacity of the battery.
A DRAM provided with a retention mode function, which decreases or bumps down the supply voltage when in a standby state, has been proposed to decrease power consumption in electronic devices. In the retention mode, after the DRAM enters a standby state and the power supply is bumped down, the internal operation is decreased to a level which is just sufficient for retaining data.
As shown in FIG. 1, a prior art DRAM 10 is formed on a semiconductor substrate (not shown) using known semiconductor integrated circuit technology. The DRAM 10 is provided with high potential and low potential external power supplies VCC, VSS (ground voltage) and operated in accordance with the levels of the external power supplies VCC, VSS. The DRAM 10 receives various signals from a controller (not shown), such as a clock signal CLK, an address signal (row and column address signal) AD, a row address strobe signal (hereafter referred to as row signal) /RAS, a column address strobe signal (hereafter referred to as column signal) /CAS, a write control signal /WE, and an output control signal /OE. When data is written, the DRAM 10 receives a data signal DI from the controller. The DRAM 10 is controlled in accordance with the state of the control signals.
The DRAM 10 includes a memory cell array 11, a row decoder 12, sense amplifiers 13, an input/output (I/O) gate 14, a column decoder 15, a sense amplifier driving circuit 16, a data input buffer 24, and a data output buffer 25. The row decoder 12 is connected to the memory cell array 11 by word lines WL0 to WLm. The sense amplifiers 13 are connected to the memory cell array 11 via a precharge circuit 30 and a transmission gate 31 by bit line pairs BL0, /BL0 to BLn, /BLn. The input/output gate 14 and the column decoder 15 are connected to the sense amplifiers 13 by the bit line pairs BL0, /BL0 to BLn, /BLn. The sense amplifiers 13 are further connected to the sense amplifier driving circuit 16 which activates the sense amplifiers 13.
The DRAM 10 also includes an address buffer pre-decoder 17, a refresh address counter 18, a mode controller 19, first and second clock generators 20, 22, and a write clock generator 23.
Furthermore, the DRAM 10 includes a substrate bias generator 26, a pull-up voltage generator 27, an internal power supply generator 28, and a reference voltage generator 29. The substrate bias generator 26 generates substrate bias power supply VBB having a level corresponding to the levels of the high potential and low potential power supplies VCC, VSS. The pull-up voltage generator 27 generates pull-up power supply VPP, which is sent to a write amplifier (not shown), in accordance with the levels of the high potential and low potential power supplies VCC, VSS. The internal power supply generator 28 generates internal power supply VDD, which is sent to each section of the DRAM 10 except for the memory cell array 11 and the write amplifier, in accordance with the levels of the high potential and low potential power supplies VCC, VSS.
As shown in FIG. 4, the reference voltage generator 29 includes a pair of high resistors 35, 36, which are connected in series between the internal power supply VDD and the low potential power supply VSS, and a compensation circuit 37. The high resistors 35, 36 have substantially the same resistance value. Reference power supplies VPR, VPD having values that are half of that of the internal power supply VDD are output from a node between the high resistors 35, 36. The reference power supply VPR is provided to the precharge circuit 30, and the reference power supply VPD is sent to the memory cell array 11.
The relationship between the voltages of the external power supplies VCC, VSS and the voltages of the substrate bias power supply VBB, the pull-up power supply VPP, the internal power supply VDD, the reference power supply VPR, and the reference power supply VPD are shown in FIG. 5.
The substrate bias power supply VBB voltage decreases so that it becomes lower than the low potential power supply VSS voltage as the external power supply VCC voltage increases. When the external power supply VCC reaches voltage VCCr, which is the value when entering the retention mode, the substrate bias power supply VBB becomes constant at a negative value.
The internal power supply VDD voltage increases proportionally to the external power supply VCC voltage so that it is equal to the external power supply VCC voltage. When the internal power supply VDD reaches a normal mode VCC range, the internal power supply VDD becomes constant at a positive value.
The pull-up power supply VPP voltage increases proportionally to the external power supply VCC voltage so that it is greater than the external power supply VCC voltage. When the pull-up power supply VPP voltage reaches the normal mode VCC range, the pull-up power supply VPP becomes constant at a value greater than the internal power supply VDD voltage.
The reference power supply VPR voltage and the reference power supply VPD voltage increase proportionally to the external power supply VCC voltage until they become one half the level of the internal power supply voltage VDD. When the external power supply VCC reaches the normal mode VCC range, the reference power supply VPR voltage and the reference power supply VPD voltage are one half the level of the internal power supply VDD voltage.
Returning to FIG. 1, the clock generator 20 receives the row signal /RAS and the column signal /CAS from the controller and controls the address buffer pre-decoder 17 in accordance with the row signal /RAS. The clock generator 20 generates an activation signal LE and a first precharge signal BRS based on the row signal /RAS and the column signal /CAS and sends the activation signal LE and the first precharge signal BRS to the sense amplifier driving circuit 16 and the precharge circuit 30, respectively. The activation signal LE is high for a predetermined time after selection of a memory cell. The first precharge signal BRS is high when memory cell selection is not being performed and low when memory cell selection is being performed.
The mode controller 19 receives the row signal /RAS from the clock generator 20 and the column signal /CAS and determines the refresh mode in accordance with the levels of the signals /CAS, /RAS. Refresh modes include a known RAS only refresh mode, a CBR refresh mode, and a self refresh mode. The mode controller 19 controls the address buffer pre-decoder 17 and the refresh address counter 18 in accordance with the determined refresh mode. The refresh address counter 18 is operated in accordance with the control signal from the mode controller 19 during the refresh mode and the self refresh mode. More specifically, the refresh address counter 18 counts the refresh address (row address) of the memory cells that should be refreshed and sends the count value to the address buffer pre-decoder 17.
An AND circuit 21 has an input terminal for receiving the column signal /CAS and the control signal from the clock generator 20 and an output terminal connected to the clock generator 22. The clock generator 22 controls the address buffer pre-decoder 17 and the column decoder 15 in accordance with the level of the output signal of the AND circuit 21. During the data reading operation, the clock generator 22 controls the output buffer 25 to output data DO, which is read from the memory cell array 11.
The address buffer pre-decoder 17 receives the address signal AD in accordance with the control signal from the clock generator 20 and sends a predecode signal PRA to the row decoder 12. Further, the address buffer pre-decoder 17 receives the address signal AD in accordance with the control signal from the clock generator 22 and sends a predecode signal PRA to the column decoder 15. The column decoder 15 decodes the predecode signal PCA from the address buffer pre-decoder 17 to a selection signal and selects the predetermined bit line pairs BL0, /BL0 to BLn, /BLn of the memory cell array 11.
The write clock generator 23 receives a signal from the clock generator 22 and a reading signal /WE from an external device and controls the data input buffer 24 so that the data input buffer 24 receives the write signal DI during the write operation.
FIG. 2 is a circuit diagram showing the memory cell array 11, the sense amplifiers 13, and the sense amplifier driving circuit 16 in detail. The memory cell array 11 is also provided with the word lines WL0 to WLm (only lines WL0, WL1, WLm-1, WLm are shown in FIG. 2) and the pairs of the bit lines BL0, /BL0 to BLn, /BLn (only BL0, /BL0, BLn, /BLn are shown). The potential at the bit line pairs BL0, /BL0 to BLn, /BLn is set at one half of the internal power supply VDD voltage. During selection of memory C, an NMOS transistor 45 is deactivated in response to a low first precharge signal BRS and disconnected from the bit line pairs BL0, /BL0 to BLn, /BLn. Furthermore, NMOS transistors 46, 47 are deactivated to complete precharging of the bit line pairs BL0, /BL0 to BLn, /BLn and complete data write/read preparation.
The bit line pairs BL0, /BL0 to BLn, /BLn are connected to the sensor amplifier 13 via the transmission gate 31. The transmission gate 31 includes NMOS transistors 31A, each of which is connected to one of the bit lines BL0, /BL0 to BLn, /BLn. A high transmission control signal BT is sent to the gate of each NMOS transistor 31A. The transmission control signal BT is generated in accordance with the pull-up voltage BT and has the same voltage as the pull-up voltage BT. Accordingly, a high transmission control signal BT activates all of the NMOS transistors 31A and connects the memory cell array 11 to the sense amplifiers 13 and the I/O gate 14.
Each sense amplifier 13 forms a latch circuit that includes a first inverter 13a and a second inverter 13b. The first inverter 13a has a PMOS transistor 40 and an NMOS transistor 41 which are connected in series between high potential and low potential power supply lines PSA, NSA. The second inverter 13b has a PMOS transistor 42 and an NMOS transistor 43 which are connected in series between high potential and low potential power supply lines PSA, NSA. The PMOS and NMOS transistors 40, 41 have gates that are connected to the output terminal of the second inverter 13b and the inverted side of the bit lines /BL0-/BLn. The PMOS and NMOS transistors 42, 43 have gates that are connected to the output terminal of the first inverter 13a and the non-inverted side of the bit lines BL0 to BLn.
The sense amplifier driving circuit 16 is connected to the high potential and low potential power supply lines PSA, NSA to activate the sense amplifiers 13. The sense amplifier driving circuit 16 has a PMOS transistor 50, NMOS transistors 51, 52, and an inverter 53. The PMOS and NMOS transistors 50, 51, 52 are connected in series between the internal potential power supply VDD and the low potential power supply VSS. The PMOS transistor 50 has a source connected to the internal power supply VDD and a drain connected to the high potential power supply line PSA. The NMOS transistor 51 has a source connected to the high potential power supply line PSA and a drain connected to the low potential power supply line NSA. The NMOS transistor 52 has a source connected to the low potential power supply VSS and a drain connected to the low potential power supply line NSA. The PMOS transistor 50 and the NMOS transistor 51 have gates for receiving a signal /LE, which is the activation signal LE inverted, via the inverter 53. The NMOS transistor 52 has a gate for receiving the activation signal LE. The activation signal LE is high for a predetermined period when the row decoder 12 selects one of the word lines WL0 to WLm and selects a memory cell C. The activation signal LE remains low when none of the word lines WL0 to WLm are selected and none of the memory cells C are selected.
Accordingly, during memory selection, in response to a high activation signal LE, the PMOS and NMOS transistors 50, 52 are activated and the NMOS transistor 51 is deactivated. The high potential power supply line PSA is connected to the internal power supply VDD in response to the activation of the PMOS transistor 50. The low potential power supply line NSA is connected to the low power supply VSS in response to the activation of the NMOS transistor 52. The difference between the high potential power supply line PSA and the low potential power supply line NSA activates the sense amplifiers 13. In accordance with the levels of the high potential and low potential power supply lines PSA, NSA, each of the sense amplifiers 13 amplify the data of the corresponding bit line pairs BL0, /BL0 to BLn, /BLn and retains the amplified data.
When the memory cell is not selected, in response to a low activation signal LE, the PMOS and NMOS transistors 50, 52 are deactivated and the NMOS transistor 51 is activated. The high potential power supply line PSA is disconnected from the internal power supply VDD in response to the deactivation of the PMOS transistor 50. The low potential power supply line NSA is disconnected from the low power supply VSS in response to the deactivation of the NMOS transistor 52. In this state, the high potential and low potential power supply lines PSA, NSA are short circuited by the NMOS transistor 51. Since the high potential and low potential power supply lines PSA, NSA have levels that are one half of the internal power supply VDD voltage, the potential difference between the power supply lines PSA, NSA becomes null. This deactivates each of the sense amplifiers 13.
The operation of the DRAM 10 will now be described.
With reference to FIG. 3, if the external power supply VCC voltage is at the voltage VCCn, which is the value when in the normal state, the DRAM 10 is set in a normal operation mode. In this state, the internal power supply VDD voltage is set at the voltage VDDn and the reference power supplies VPR, VPD voltages are both set at a value represented by VDD/2.
[Read Operation Mode]
With reference to FIG. 1, when the DRAM 10 receives a high write control signal /WE, the DRAM 10 enters the read operation mode. When the row signal /RAS is high, the first precharge signal BRS is high. Accordingly, the precharge circuit 30 is activated causing the potential at the bit line pairs BL0, /BL0 to BLn, /BLn to be VDDn/2. In this state, since the activation signal LE is low, the sense amplifier driving circuit 16 is deactivated thereby causing the voltages at the high potential and low potential power supply lines PSA, NSA to be VDDn/2.
When the row signal /RAS falls, the first precharge signal BRS becomes low. This deactivates the precharge circuit 30 and disconnects the pairs of bit lines BL0, /BL0 to BLn, /BLn.
When the row signal /RAS falls, the address signal AD is sent to the address buffer pre-decoder 17 and decoded into a predecode signal PRA. When the column signal /CAS falls, the address signal AD is sent to the address buffer precharge decoder 17 and decoded into a predecode signal PCA.
The predecode signal PRA is decoded into a first selection signal by the row decoder 12. A predetermined word line WL0 to WLm is selected in accordance with the first selection signal. The predecode signal PCA is decoded into a second selection signal by the column decoder 15. A predetermined bit line pair BL0, /BL0 to BLn, /BLn is selected in accordance with the second selection signal. The data of the memory cell C connected to the selected word line WL0 to WLm and bit line pair BL0, /BL0 to BLn, /BLn is read out to the associated bit line BL0, /BL0 to BLn, /BLn. The read data is transmitted to the corresponding sense amplifier 13 via the transmission gate 31.
In response to a high activation signal LE, the sense amplifier driving circuit 16 is activated, the high potential power supply line PSA voltage is set at the voltage VDDn of the internal power supply VDD, and the low potential power supply line NSA is set at the low potential power supply VSS voltage (ground potential). Each sense amplifier 13 is activated in accordance with the high potential and low potential power supply lines PSA, NSA. The sense amplifiers 13 amplify the data of the associated bit line pair BL0, /BL0 to BLn, /BLn and retain the amplified data. The amplified data is transmitted to the data output buffer 25 via the I/O gate 14.
The transmitted data is output by the data output buffer 25 as read data DO in response to the output control signal /OE.
[Write Operation Mode]
When the DRAM 10 receives a low write control signal /WE, the DRAM 10 enters the write operation mode. When the row signal /RAS is high, the first precharge signal BRS is high and the level at the bit line pairs BL0, /BL0 to BLn, /BLn is VDDn/2. In this state, since the activation signal LE is low, the sense amplifier driving circuit 16 is deactivated thereby causing the voltage at the low potential and high potential power supply lines PSA, NSA to be VDDn/2.
When the row signal /RAS falls, the first precharge signal BRS becomes low. This deactivates the precharge circuit 30 and disconnects the pairs of bit lines BL0, /BL0 to BLn, /BLn.
When the row signal /RAS falls, the address signal AD is sent to the address buffer pre-decoder 17 and decoded into the predecode signal PRA. When the column signal /CAS falls, the address signal AD is sent to the address buffer precharge decoder 17 and decoded into the predecode signal PCA.
The predecode signal PRA is decoded into a first selection signal by the row decoder 12. A predetermined word line WL0 to WLm is selected in accordance with the first selection signal. The predecode signal PCA is decoded into a second selection signal by the column decoder 15. A predetermined bit line pair BL0, /BL0 to BLn, /BLn is selected in accordance with the second selection signal.
In response to the write control signal /WE, a write signal DI is sent to the data input buffer 24. The write signal DI is transmitted to the memory cell array 11 via the I/O gate 14 and the transmission gate 31. The write signal DI is then written to the memory cell C connected to the selected word line WL0 to WLm and the selected pairs of bit lines BL0, /BL0 to BLn, /BLn.
[Refresh Mode]
The DRAM 10 enters the refresh mode when only the row signal /RAS falls or when the row signal /RAS falls after the column signal /CAS falls.
When the row signal /RAS is high, the first precharge signal BRS is high. Accordingly, the precharge circuit 30 is activated causing the level at the bit line pairs BL0, /BL0 to BLn, /BLn to be VDDn/2. In this state, since the activation signal LE is low, the sense amplifier driving circuit 16 is deactivated thereby causing the high potential and low potential power supply line PSA, NSA voltages to be VDDn/2.
When the row signal /RAS falls, the first precharge signal BRS becomes low. This deactivates the precharge circuit 30 and disconnects the pairs of bit lines BL0, /BL0 to BLn, /BLn.
When the row signal /RAS falls, the address signal AD is sent to the address buffer pre-decoder 17 and decoded into a predecode signal PRA. The predecode signal PRA is decoded into a first selection signal by the row decoder 12. A predetermined word line WL0 to WLm is selected in accordance with the first selection signal. All of the data of the memory cells C connected to the selected word line WL0 to WLm and bit line pair BL0, /BL0 to BLn, /BLn is read out to each of the bit lines BL0, /BL0 to BLn, /BLn. The read data from the selected memory cells C is transmitted to the corresponding sense amplifier 13 via the transmission gate 31.
In response to a high activation signal LE, the sense amplifier driving circuit 16 is activated, the high potential power supply line PSA voltage is set at the voltage VDDn, and the low potential power supply line NSA is set at the low potential power supply VSS voltage (ground potential). Each sense amplifier 13 is activated in accordance with the high potential and low potential power supply lines PSA, NSA. The sense amplifiers 13 amplify the data of the associated bit line pair BL0, /BL0 to BLn, /BLn. The amplified data is transmitted via the bit line pairs BL0, /BL0 to BLn, /BLn and written on the corresponding memory cells C. This completes the refreshing of a single line.
In the refresh mode, a different word line WL0 to WLm is selected each time the row signal /RAS falls. The data on all of the memory cells connected to the selected word line WL0 to WLm is refreshed.
[Retention Mode]
With reference to FIG. 3, if the high potential power supply VCC is bumped down when the DRAM 10 is in a standby state, the DRAM 10 enters a retention mode. During the retention mode, only refreshing of the memory cell array 11 is performed. The refreshing of the memory cell array 11 is performed in the same manner as when in the normal operation mode.
In the DRAM 10, the sense amplifiers 13 are designed so that they are operated based on the reference power supply VPR voltage and so that if the reference power supply VPR voltage is equal to the sense amplifier power supply (i.e., one half of the internal power supply VDD voltage), the sense amplifiers 13 perform amplifying in a satisfactory manner.
However, the DRAM 10 generates the reference power supplies VPR, VPD when the internal power supply VDD is pulled down and sends the reference power supplies VPR, VPD via wires to the memory cell array 11. Thus, the reference power supply VPR voltage is not accurately set at one half the voltage of the internal power supply VDD. If the cell data is amplified and the voltage between the pairs of bit lines BL, /BL is maximized, the accurate value of the reference power supply VPR voltage is (VBL1+VBL2)/2.
In this manner, if the reference power supply VPR voltage is offset from a value that is one half the internal power supply VDD voltage, the reading characteristic of the sense amplifiers 13 is degraded. If the reference power supply VPR voltage is higher than a predetermined range that includes the value corresponding to one half the internal power supply VDD voltage, the data stored in the memory cell C may be destroyed.
For example, if the memory cell array 11 is refreshed immediately after the DRAM 10 enters the retention mode, the data stored in the memory cell C may be destroyed.
In other words, when the DRAM 10 is in the retention mode, if the external power supply VCC voltage decreases, the internal power supply VDD voltage decreases accordingly so that the voltage VDDr of the internal power supply VDD becomes equal to the voltage VCCr of the external power supply VCC. Hence, the reference voltage of the sense amplifiers 13 is set at VDDr/2.
The reference power supplies VPR, VPD are generated by pulling down the internal power supply VDD with the reference potential generator 29. The driving force of the reference potential generator 29 is low, and the parasitic capacitance of the sense amplifiers 13 and the pairs of bit lines BL0, /BL0 to BLn, /BLn is large for the power supply VPR. Thus, the reference power supply VPR, VPD voltages do not decrease in accordance with the voltage decrease of the external power supply and gradually decrease to VDDr/2 at a predetermined rate (several hundred microseconds). Accordingly, during this period, the reference power supply VPR, VPD voltages are set at a value greater than the reference voltages VDDr/2 of the sense amplifiers 13. Hence, if the memory cell array 11 is refreshed before the reference power supply VPR voltage reaches VDDr/2, the data stored in the memory cells C may be destroyed.
To overcome this problem, a DRAM or a DRAM controller can be provided with a timer. When the DRAM enters the retention mode, the timer measures the time until the reference power supply VPR, VPD voltages become one half the voltage of the internal power supply VDD and the issuance of a refresh command during that period is prohibited.
However, in the DRAM 10 provided with the retention mode, for example, the change from the normal operation of the internal power supply VDD (VDDn=2.5V) to the retention mode (VDDr=1.5V) is relatively large. Further, the operational ambient temperature of the DRAM 10 and the controller is between 0.degree. C. to 75.degree. C. Thus, the production of a highly accurate timer for measuring several hundred microseconds on the semiconductor device is impossible. Further, such a timer is a complicated analog circuit that occupies a large circuit area. Accordingly, the circuit area of the semiconductor device increases. This, in turn, increases production costs.
Furthermore, in the retention mode, a standby time of several hundred microseconds before commencing refreshing is relatively long in comparison to the data retention time of several milliseconds. Thus, refreshing must be performed in a concentrated manner just before entering the retention mode to retain the data of the DRAM 10 in the retention mode. This increases the current consumption of the DRAM 10 and complicates the control of the DRAM 10.
In the normal operation mode of the DRAM 10, a reference potential need not be applied to the selected bit line pairs BL0, /BL0 to BLn, /BLn to perform the write operation. In this case, only a potential difference in the write signal, which is applied to the selected bit line pairs BL0, /BL0 to BLn, BLn, need occur. In the write operation, the precharge circuit 30 is activated each time data is written. This precharges the pairs of bit lines BL0, /BL0 to BLn, /BLn in accordance with the reference power supply VPR and causes the potentials of each bit line pair BL0, /BL0 to BLn, /BLn to be equal to each other. As described above, the drive power of the reference potential generator 29 is low, and the reference power supplies VPR, VPD are sent to the entire memory cell array 11. Thus, when the pairs of bit lines BL0, /BL0 to BLn, /BLn are precharged after the data is written, the voltage of the reference power supply VPR becomes one half the total of the voltages of pairs of bit lines BL0, /BL0 to BLn, /BLn. Accordingly, if the write operation is performed consecutively for N times, the voltage of the write signal of the pairs of bit lines BL0, /BL0 to BLn, /BLn subsequent to the precharging may be offset greatly from the reference voltage VDDn/2 of the sense amplifiers 13.
Therefore, if the read operation is performed immediately after the write operation is performed consecutively for N times, the sense amplifiers 13 may not function properly and may thus destroy the data of the selected memory cell C.